封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NBG36 |
| Lead Count (#): | 36 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.75 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 36 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | AUSTRIA |
| Additive Phase Jitter Typ RMS (fs) | 34.7 |
| Core Voltage (V) | 3.3V, 2.5V |
| Family Name | 8T39S |
| Function | Buffer |
| Input Freq (MHz) | 2000 |
| Input Type | Crystal, HCSL, LVDS, LVPECL, HSTL, LVCMOS |
| Inputs (#) | 3 |
| Length (mm) | 6 |
| MOQ | 2500 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 2000 |
| Output Skew (ps) | 32 |
| Output Type | HCSL, LVDS, LVPECL |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 6 |
| Package Area (mm²) | 36 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.75 |
| Pkg. Type | VFQFPN |
| Product Category | Clock Buffers & Drivers |
| Prog. Interface | Pin select |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 0.75 |
| Width (mm) | 6 |
| 已发布 | No |
有关 8T39S06A 的资源
描述
The 8T39S06A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to six differential outputs which can be configured as LVPECL, LVDS, or HCSL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.