特性
- Four banks of two low skew outputs
- Selectable bank output divider values: ÷1 through ÷6 and ÷8
- Individual outputs remain enabled while serial loading new device configurations
- One differential PCLK, nPCLK input
- PCLK, nPCLK input pair can accept the following differential input levels: LVPECL, LVDS, or CML levels
- Maximum input frequency: 1.5GHz
- LVCMOS control inputs
- QXx ÷1 edge aligned to QXx ÷n edge
- Individual output divider control via serial interface
- Individual output enable/disable control via serial interface
- Individual output type control, LVDS or LVPECL, via serial interface
- 2.375V to 3.465V supply voltage operation
- -40 °C to 85 °C ambient operating temperature
- Available in lead-free (RoHS 6) package
描述
The 8T79S828-08I is a high-performance, 1-to-8, differential input to universal output clock divider and fanout buffer. The device is designed for frequency-division and signal fanout of high-frequency clock signals in applications requiring four different output frequencies generated simultaneously. Each bank of two outputs has a selectable divider value of ÷1 thru ÷6 and ÷8. The 8T79S828-08I is optimized for 3.3V and 2.5V supply voltages and a temperature range of -40 °C to 85 °C. The device is packaged in a space saving 32-lead VFQFN package.
产品参数
| 属性 | 值 |
|---|---|
| Function | Buffer, Divider |
| Outputs (#) | 8 |
| Output Type | LVPECL, LVDS |
| Output Freq Range (MHz) | 1500 |
| Input Type | LVPECL, LVDS, CML |
| Output Banks (#) | 4 |
| Output Voltage (V) | 2.5V, 3.3V |
| Output Skew (ps) | 80 |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 32 | 0.5 |