封装信息
| Lead Count (#) | 88 |
| Pkg. Code | NLG88 |
| Pitch (mm) | 0.4 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 0.9 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Lead Count (#) | 88 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Country of Assembly | Taiwan |
| Country of Wafer Fabrication | Singapore, United States |
| Accepts Spread Spec Input | No |
| Additive Phase Jitter Typ RMS (fs) | 63.1 |
| Additive Phase Jitter Typ RMS (ps) | 0.063 |
| Adjustable Phase | Yes |
| Advanced Features | Holdover, Phase Delay, Input Switching, JESD204B, Programmable Clock |
| Channels (#) | 1 |
| Core Voltage (V) | 3.3 |
| DPLL Channels (#) | 0 |
| Feedback Divider Resolution (bits) | 12 |
| Fractional Output Dividers (#) | 0 |
| Frequency Plan | 2949.12 / Output_Divider |
| Input Freq (MHz) | 1.92 - 2000 |
| Input Redundancy | Input Monitor, Auto-switch, Manual switch, Revertive and non-revertive switch, Holdover |
| Input Ref. Divider Resolution (bits) | 12 |
| Input Type | LVDS, LVPECL |
| Inputs (#) | 2 |
| JESD204B/C Compliant | Yes |
| Length (mm) | 10 |
| Loop Bandwidth Range (Hz) | 20 - 100 |
| MOQ | 2500 |
| Noise Floor (dBc/Hz) | -160 |
| Output Banks (#) | 5 |
| Output Divider Resolution (bits) | 8 |
| Output Freq Range (MHz) | 18.432 - 2949.12 |
| Output Skew (ps) | 0 |
| Output Type | LVDS, LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 15 |
| PLL | Yes |
| Package Area (mm²) | 64.0 |
| Phase Jitter Typ RMS (fs) | 63.100 |
| Phase Jitter Typ RMS (ps) | 0.063 |
| Phase Noise Supports GSM | Yes |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Ports (#) | 1 |
| Product Category | JESD204B/C |
| Prog. Clock | Yes |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Synthesis Mode | Integer |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 10 |
| Xtal Freq (KHz) | 30720 - 250000 |
描述
The 8V19N492 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.
A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.
The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The 8V19N492 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT.
For information regarding evaluation boards and material, please contact your local sales representative.