特性
- Digital PLL synchronizes with Ethernet connected synchronization sources
- DPLL bandwidth is 1.2 Hz; DPLL holdover accuracy is 1.1X10-5 ppm
- Input references are monitored for frequency offset and activity
- DPLL holdover, free run and hitless reference switching can be forced by the host processor or can be automatically controlled by an internal state machine
- Internal DCO has resolution of 0.01105 ppb and can be controlled by an external processor via I2C interface for IEEE 1588 clock generation
- One Analog PLL for jitter attenuation
- Jitter generation <0.65ps RMS (10 kHz to 20 MHz), meets jitter requirements of 1 GbE PHYs and QSGMII
- IN1, IN2 and IN3 accept single ended reference clocks whose frequencies can be 25 MHz, 125 MHz or 156.25 MHz
- OUT1 outputs a differential clock with frequency of 125 MHz or 156.25 MHz
- OUT2 to OUT6 output differential clocks all with the same frequency of 125 MHz or 156.25 MHz
- OUT7 outputs a free-running LVCMOS clock with frequency of 25 MHz
描述
The IDT8V89316 is used to frequency synchronize equipment with an Ethernet connected reference; its integrated DCO (Digitally Controlled Oscillator) can be controlled by an external IEEE 1588 clock recovery servo to synthesize IEEE 1588-based clocks. The IDT8V89316 low jitter output clocks can be used to directly time Gigabit Ethernet PHYs and QSGMII devices.