封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SSOP |
| Pkg. Code: | PYG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 10.2 x 5.3 x 1.73 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
产品属性
| Pkg. Type | SSOP |
| Lead Count (#) | 28 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Accepts Spread Spec Input | Yes |
| Advanced Features | Accepts Spread Spec Input, Spread Spectrum |
| C-C Jitter Max P-P (ps) | 65 |
| Clock Spec. | DDR1 |
| Core Voltage (V) | 2.5 |
| Die Form | No |
| Diff. Input Signaling | DDR1 |
| Diff. Output Signaling | DDR1 |
| Input Freq (MHz) | 66 - 200 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 10.2 |
| MOQ | 235 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 66 - 200 |
| Output Skew (ps) | 100 |
| Output Type | LVPECL |
| Output Voltage (V) | 2.5 |
| Outputs (#) | 6 |
| Package Area (mm²) | 54.1 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 75 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 10.2 x 5.3 x 1.73 |
| Qty. per Carrier (#) | 47 |
| Qty. per Reel (#) | 0 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 2.5 - 2.5 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1.73 |
| Width (mm) | 5.3 |
有关 93722 的资源
描述
DDR Zero Delay Clock Buffer