瑞萨电子 (Renesas Electronics Corporation)
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9DB106

有效

6-output Differential Buffer For PCIe Gen2

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特性

  • 6 - 0.7 V current mode differential output pairs (HCSL)
  • CLKREQ# pin for outputs 1 and 4/ supports Express Card applications
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled
  • Cycle-to-cycle jitter < 50 ps
  • Output-to-output skew < 50 ps
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9DB106 - Block Diagram
9DB106 - Pinout
9DB106 - Block Diagram
9DB106 - Pinout

描述

The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.

产品参数

属性 值
Temp. Range (°C) -40 to 85°C, 0 to 70°C

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
TSSOP 9.7 x 4.4 x 1.0 28 0.65

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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