瑞萨电子 (Renesas Electronics Corporation)
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9DB108

过时

8-Output Differential Buffer for PCIe Gen 1

注意 - 建议使用以下设备作为替代品：
9DBL0841 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL0851 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DB803 - 8-output Differential Buffer for PCIe Gen2

概览

The 9DB108 8-output differential buffer for PCIe Gen 1 is not recommended for new designs. The 9DB803 8-output differential buffer for PCIe Gen 2 is the recommended replacement.

  • Supports tight ppm accuracy clocks for Serial-ATA
  • Spread spectrum modulation tolerant, 0% to -0.5% down spread and ± 0.25% center spread
  • Supports undriven differential output pair in PD# and SRC_STOP# for power management

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设计和开发

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点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。

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视频和培训

PCIe Clocking Architectures (Common and Separate)

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below

Video List
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview