特性
- Supports tight ppm accuracy clocks for Serial-ATA
- Spread spectrum modulation tolerant, 0% to -0.5% down spread and ± 0.25% center spread
- Supports undriven differential output pair in PD# and SRC_STOP# for power management
描述
The 9DB108 8-output differential buffer for PCIe Gen 1 is not recommended for new designs. The 9DB803 8-output differential buffer for PCIe Gen 2 is the recommended replacement.
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.