概览
描述
The 9DB233 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while two clock request (OE#) pins make the 9DB233 suitable for Express Card applications.
特性
- Two 0.7V HCSL differential output pairs
- Phase jitter: PCIe Gen3 < 1ps rms
- Phase jitter: PCIe Gen2 < 3.1ps rms
- Phase jitter: PCIe Gen1 < 86ps peak-to-peak
- Supports Zero Delay Buffer mode and Fanout mode
- Bandwidth programming available
- 33MHz to 110MHz operation in PLL mode
- 10MHz to 110MHz operation in Bypass mode
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| 模型 - IBIS | ZIP 11 KB | |
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视频和培训
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
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