封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 9.7 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 28 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 50 |
| Package Area (mm²) | 42.7 |
| Pkg. Dimensions (mm) | 9.7 x 4.4 x 1.0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Accepts Spread Spec Input | Yes |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2 |
| Architecture | Common |
| C-C Jitter Max P-P (ps) | 25 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | LVPECL, LVDS, LVHSTL, SSTL, HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LVPECL |
| Diff. Outputs | 6 |
| Diff. Termination Resistors | 24 |
| Feedback Input | No |
| Input Freq (MHz) | 90 - 140 |
| Input Type | HCSL, HSTL, LVDS, LVPECL, SSTL |
| Inputs (#) | 1 |
| Length (mm) | 9.7 |
| MOQ | 100 |
| Output Banks (#) | 6 |
| Output Freq Range (MHz) | 90 - 140 |
| Output Skew (ps) | 100 |
| Output Type | LVPECL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 6 |
| PLL | Yes |
| Phase Jitter Typ RMS (ps) | 3 |
| Pitch (mm) | 0.65 |
| Pkg. Type | TSSOP |
| Prog. Clock | No |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
| 已发布 | No |
有关 9DB306 的资源
描述
The 9DB306 is a high performance 1-to-6 Differential-to- LVPECL Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. There is also a high bandwidth mode which sets the PLL bandwidth at 1MHz which will pass more spread spectrum modulation. For SerDes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI Express Applications.