特性
- PCIe Gen 1–4 CC compliant
- Supports PCIe Gen 2–3 SRIS compliant
- Supports PCIe SRnS compatible
- Direct connection to 100Ω transmission lines; saves 28 resistors compared to standard PCIe devices
- Spread spectrum tolerant; allows reduction of EMI
- Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Easy AC coupling to other logic families; see the application note AN-891.
- Space saving 5mm x 5mm 40-VFQFPN; minimal board space
9DBL07 Block Diagram
描述
The 9DBL0741 7-output 3.3V PCIe fanout clock buffer is a member of Renesas' 3.3V full-featured PCIe clock family. The 9DBL0741 supports PCIe Gen 1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. The device's integrated output terminations provide a direct connection to 100Ω transmission lines. The 9DBL07P1 can be factory programmed with a user-defined power-up default SMBus configuration.
For information regarding evaluation boards and material, please contact your local sales representative.
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 7 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 200 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 134 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 25 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 1 - 200 |
| Additive Phase Jitter Typ RMS (fs) | 300 |
| Function | Fanout Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
