瑞萨电子 (Renesas Electronics Corporation)
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9DBL411

有效

4-Output 3.3V PCIe Gen1-2-3 Fanout Buffer

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特性

  • Four low-power differential output pairs
  • Individual OE# control of each output pair
  • Output cycle-cycle jitter < 25ps additive
  • Output-to-output skew: < 50ps
  • Low-power differential fanout buffer for PCI Express and CPU clocks
  • Available in commercial (0 °C to +70 °C) and industrial (-40 °C to +85 °C) temperature ranges
  • Available in 20-VFQFPN or 20-TSSOP packages
查找应用特定型时钟的其他产品
9DBL411B - Block Diagram
9DBL411B - Pin Assignment (20-VFQFPN)
9DBL411B - Pin Assignment (20-TSSOP)
9DBL411B - Block Diagram
9DBL411B - Pin Assignment (20-VFQFPN)
9DBL411B - Pin Assignment (20-TSSOP)

描述

The 9DBL411 is a four-output lower power differential buffer. Each output has its own OE# pin. The device has a maximum operating frequency of 150MHz.

产品参数

属性值
Temp. Range (°C)-40 to 85°C, 0 to 70°C

封装选项

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
TSSOP6.5 x 4.4 x 1.0200.65

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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