特性
- LP-HCSL outputs; save 4 resistors compared to standard HCSL outputs
- 35mW typical power consumption in PLL mode; minimal power consumption
- Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- SMBus-selectable features; optimize signal integrity to application
- Slew rate for each output
- Differential output amplitude
- Pin/Software selectable PLL bandwidth and PLL bypass; minimize phase jitter for each application
- Outputs are blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 24-pin 4mm x 4mm VFQFPN; minimal board space
描述
The 9DBV0231 very-low power, 2-output, 1.8V, PCIe zero-delay/fanout clock buffer has two output enables for clock management.
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 30 - 137.5 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 52 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 4 |
| Package Area (mm²) | 16 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 30 - 175 |
| Divider Value | 1 |
| Additive Phase Jitter Typ RMS (fs) | 250 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8 |
| Output Voltage (V) | 0.8 |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 4.0 x 4.0 x 0.9 | 24 | 0.5 |
应用
- 1.8V PCIe Gen 1–5 Zero-Delay/Fanout Buffer (ZDB/FOB)