封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Assembly Location | MALAYSIA |
| Wafer Fab Location | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 250 |
| Additive Phase Jitter Typ RMS (ps) | 0.25 |
| Advanced Features | Multiple SMBus addresses |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 1.8V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 2 |
| Diff. Termination Resistors | 0 |
| Divider Value | 1 |
| Feedback Input | No |
| Function | Zero Delay Buffer |
| Input Freq (MHz) | 30 - 175 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| Longevity | 2040 四月 |
| MOQ | 490 |
| NXP Processor Function | SerDes Clock |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 30 - 137.5 |
| Output Impedance | 100 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.8V |
| Outputs (#) | 2 |
| PLL | Yes |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 52 |
| Product Category | PCI Express Clocks |
| Prog. Clock | No |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 4 |
有关 9DBV0241 的资源
描述
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management.