特性
- LP-HCSL outputs; save 18 resistors and 31mm² compared to standard HCSL
- PCIe Gen 1–5 compliance
- 53mW typical power consumption; eliminates thermal concerns
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- SMBus-selectable features allow optimization to customer requirements
- Slew rate for each output; allows tuning for various line lengths
- Differential output amplitude; allows tuning for various application environments
- 1MHz to 200MHz operating frequency
- 3.3V tolerant SMBus interface works with legacy controllers
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
- Device contains default configuration; SMBus interface is not required for device operation
- Space-saving 6mm x 6mm 48-pin VFQFPN; minimal board space
描述
The 9DBV0931 1.8V PCIe fanout clock buffer has nine output enables for clock management and three selectable SMBus addresses.