封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 32 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common, SRNS |
| Output Impedance | 100 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Spread Spectrum, Reference Output |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 4 |
| Diff. Termination Resistors | 0 |
| Function | Generator |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 5 |
| MOQ | 2500 |
| NXP Processor Function | SerDes Clock |
| Output Freq Range (MHz) | 25 - 25, 100 - 100 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL, LVCMOS |
| Output Voltage (V) | 0.8V, 3.3V |
| Outputs (#) | 5 |
| PLL | Yes |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 142 |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (MHz) | 25 - 25 |
| Xtal Inputs (#) | 1 |
| 已发布 | No |
有关 9FGL04 的资源
描述
The 9FGL0441/51 devices are 4-output 3.3V PCIe Gen 1–6 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0441/51 supports PCIe Gen 1–6 Common Clocked architectures (CC), PCIe Separate Reference no Spread (SRNS), and Separate Reference Independent Spread (SRIS) clocking architectures.