封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NDG40 |
| Lead Count (#): | 40 |
| Pkg. Dimensions (mm): | 5.0 x 5.0 x 0.9 |
| Pitch (mm): | 0.4 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 40 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6 |
| Architecture | Common, SRNS, SRIS |
| Output Impedance | 100 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Assembly Location | TAIWAN |
| Wafer Fab Location | TAIWAN |
| Advanced Features | Spread Spectrum, Reference Output |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3V |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 6 |
| Diff. Termination Resistors | 0 |
| Function | Generator |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Lead Compliant | No |
| Length (mm) | 5 |
| Longevity | 2040 四月 |
| MOQ | 490 |
| NXP Processor Function | SerDes Clock |
| Output Freq Range (MHz) | 25 - 25, 100 - 100 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL, LVCMOS |
| Output Voltage (V) | 0.8V, 3.3V |
| Outputs (#) | 7 |
| PLL | Yes |
| Package Area (mm²) | 25 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 5.0 x 5.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 78 |
| Price (USD) | $3.6498 |
| Product Category | PCI Express Clocks |
| Prog. Clock | No |
| Reference Output | Yes |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 5 |
| Xtal Freq (MHz) | 25 - 25 |
| Xtal Inputs (#) | 1 |
有关 9FGL06 的资源
描述
The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen 1–6 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen 1–6 Common Clocked architectures (CC), PCIe Separate Reference no Spread (SRNS), and Separate Reference Independent Spread (SRIS) clocking architectures.
For information regarding evaluation boards and material, please contact your local sales representative.