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特性

  • Integrated terminations provide 100Ω differential Zo; reduced component count and board space
  • 1.8V operation; reduced power consumption
  • OE# pins; support DIF power management
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs are blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25MHz crystal; supports tight ppm with 0ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space saving 5mm x 5mm 32-VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment

描述

The 9FGV0441 is a 4-output very-low power clock generator for PCIe Gen 1–4 applications with integrated output terminations providing Zo = 100Ω. The device has four output enables for clock management and supports two different spread spectrum levels in addition to spread off.

产品参数

属性
Function Generator
Architecture Common
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4
Diff. Outputs 4
Diff. Output Signaling LP-HCSL
Output Impedance 100
Power Consumption Typ (mW) 58
Supply Voltage (V) -
Advanced Features Spread Spectrum, Reference Output

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 5.0 x 5.0 x 0.9 32 0.5

应用方框图

System on Module (SoM) Block Diagram
RZ/G2E 电源和时序系统级模块
电源和时序系统级模块(SoM)确保精确的时序和高效的功率分配。

当前筛选条件

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

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