封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | LGA |
| Pkg. Code: | LTG24 |
| Lead Count (#): | 24 |
| Pkg. Dimensions (mm): | 4.0 x 4.0 x 1.4 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 24 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Type | LVCMOS, LP-HCSL, LVDS |
| Advanced Features | 2 Reference Outputs, Spread Spectrum, Programmable Clock |
| Core Voltage (V) | 1.8V, 2.5V, 3.3V |
| Input Freq (MHz) | 8 - 50 |
| Outputs (#) | 6 |
| Output Freq Range (MHz) | 10 - 325 |
| Output Impedance | 85, 100 |
| Output Voltage (V) | 1.8V, 2.5V, 3.3V |
| Pkg. Dimensions (mm) | 4.0 x 4.0 x 1.4 |
| Prog. Clock | No |
| Qty. per Reel (#) | 0 |
| Supply Voltage (V) | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 |
| Qty. per Carrier (#) | 490 |
| Xtal Freq (MHz) | 8 - 50 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e4 Au |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | Yes |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4 |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 50 |
| Diff. Output Signaling | LP-HCSL, LVDS |
| Diff. Outputs | 4 |
| Family Name | PhiClock |
| Function | Generator |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 4 |
| MOQ | 490 |
| Output Banks (#) | 3 |
| Package Area (mm²) | 25 |
| Phase Jitter Typ RMS (ps) | 0.267 |
| Pitch (mm) | 0.5 |
| Pkg. Type | LGA |
| Power Consumption Typ (mW) | 125 |
| Product Category | PhiClock, PCI Express Clocks, Programmable Clocks |
| Prog. Interface | I2C, OTP |
| Reference Output | No |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Thickness (mm) | 1.4 |
| Width (mm) | 4 |
| Xtal Inputs (#) | 1 |
有关 9FGV1004 的资源
描述
The 9FGV1004 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1004 provides 1 copy each of 2 integer-related frequencies, 2 copies of a fractional or spread-spectrum frequency and 2 copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.