特性
- PCIe Gen1–4 compliant
- 267fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
- 4 programmable output pairs plus 2 LVCMOS REF outputs
- 2 integer and 1 fractional or spread-spectrum output per configuration
- 1MHz–325MHz integer outputs (LVDS or LP-HCSL)
- 1MHz–200MHz integer outputs (LVCMOS
- 1.8V to 3.3V core VDD
- Individual 1.8V to 3.3V VDDO for each programmable output pair
- Supports HCSL, LVDS and LVCMOS I/O standards
- Supports AC-coupled LVPECL and CML logic – see AN-891
- 4 × 4 mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
- Supported by Timing Commander™ software
描述
The 9FGV1004 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1004 provides 1 copy each of 2 integer-related frequencies, 2 copies of a fractional or spread-spectrum frequency and 2 copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
试用自定义部件配置工具。
产品参数
| 属性 | 值 |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | LP-HCSL, LVDS |
| Output Freq Range (MHz) | 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 125 |
| Supply Voltage (V) | 1.8 - 1.8, 3.3 - 3.3 |
| Output Type | LP-HCSL, LVDS |
| Xtal Freq (MHz) | 50 - 50 |
| Package Area (mm²) | 25 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 50 - 50 |
| Function | Generator |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 3 |
| Core Voltage (V) | 1.8V, 3.3V |
| Output Voltage (V) | 1.8V, 3.3V |
| Product Category | PhiClock, PCI Express Clocks, Programmable Clocks |
试用自定义部件配置工具。
| Part Number | Status | Samples | Longevity | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Output Type | Advanced Features | Core Voltage (V) | Input Freq (MHz) | Outputs (#) | Output Freq Range (MHz) | Output Impedance | Output Voltage (V) | Pkg. Dimensions (mm) | Prog. Clock | Qty. per Reel (#) | Supply Voltage (V) | Qty. per Carrier (#) | Xtal Freq (MHz) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9FGV1004C001NBGI | Active | Available | 2040 Apr | Out of Stock | VFQFPN | 24# | Tray | 1 | LP-HCSL, LVDS | 1.8V, 3.3V | 50 - 50 | 4# | 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 | 100 | 1.8V, 3.3V | 4.0 x 4.0 x 0.8 | Yes | 0 | 1.8 - 1.8, 3.3 - 3.3 | 490# | 50 - 50 | Yes | e3 Sn | -40 to 85°C | |
| 9FGV1004C001NBGI8 | Active | N/A | 2040 Apr | Out of Stock | VFQFPN | 24# | Reel | 1 | LP-HCSL, LVDS | 1.8V, 3.3V | 50 - 50 | 4# | 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 | 100 | 1.8V, 3.3V | 4.0 x 4.0 x 0.8 | Yes | 2500# | 1.8 - 1.8, 3.3 - 3.3 | 0 | 50 - 50 | Yes | e3 Sn | -40 to 85°C | |
| 9FGV1004CQ501LTGI | Active | Available | 2040 Apr | Out of Stock | LGA | 24# | Tray | 3 | LP-HCSL, LVDS | Programmable Clock | 1.8V, 3.3V | 50 - 50 | 6# | 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 | 100 | 1.8V, 3.3V | 4.0 x 4.0 x 1.4 | Yes | 0 | 1.8 - 1.8, 3.3 - 3.3 | 490# | 50 - 50 | Yes | e4 Au | -40 to 85°C |
| 9FGV1004CQ501LTGI8 | Active | N/A | 2040 Apr | Out of Stock | LGA | 24# | Reel | 3 | LP-HCSL, LVDS | Programmable Clock | 1.8V, 3.3V | 50 - 50 | 6# | 50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25 | 100 | 1.8V, 3.3V | 4.0 x 4.0 x 1.4 | Yes | 2500# | 1.8 - 1.8, 3.3 - 3.3 | 0 | 50 - 50 | Yes | e4 Au | -40 to 85°C |
| 9FGV1004B000NBGI | Obsolete | N/A | Out of Stock | VFQFPN | 24# | Tray | 1 | LVCMOS, LP-HCSL, LVDS | 2 Reference Outputs, Spread Spectrum, Programmable Clock | 1.8V, 2.5V, 3.3V | 8 - 50 | 6# | 10 - 325 | 85, 100 | 1.8V, 2.5V, 3.3V | 4.0 x 4.0 x 0.8 | No | 0 | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 | 490# | 8 - 50 | Yes | e3 Sn | -40 to 85°C | |
| 9FGV1004B000NBGI8 | Obsolete | N/A | Out of Stock | VFQFPN | 24# | Reel | 1 | LVDS, LP-HCSL, LVCMOS | 2 Reference Outputs, Spread Spectrum, Programmable Clock | 1.8V, 2.5V, 3.3V | 8 - 50 | 6# | 10 - 325 | 85, 100 | 1.8V, 2.5V, 3.3V | 4.0 x 4.0 x 0.8 | No | 2500# | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 | 0 | 8 - 50 | Yes | e3 Sn | -40 to 85°C | |
| 9FGV1004BQ500LTGI | Obsolete | N/A | Out of Stock | LGA | 24# | Tray | 3 | LVCMOS, LP-HCSL, LVDS | 2 Reference Outputs, Spread Spectrum, Programmable Clock | 1.8V, 2.5V, 3.3V | 8 - 50 | 6# | 10 - 325 | 85, 100 | 1.8V, 2.5V, 3.3V | 4.0 x 4.0 x 1.4 | No | 0 | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 | 490# | 8 - 50 | Yes | e4 Au | -40 to 85°C | |
| 9FGV1004BQ500LTGI8 | Obsolete | N/A | Out of Stock | LGA | 24# | Reel | 3 | LVCMOS, LP-HCSL, LVDS | 2 Reference Outputs, Spread Spectrum, Programmable Clock | 1.8V, 2.5V, 3.3V | 8 - 50 | 6# | 10 - 325 | 85, 100 | 1.8V, 2.5V, 3.3V | 4.0 x 4.0 x 1.4 | No | 2500# | 1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3 | 0 | 8 - 50 | Yes | e4 Au | -40 to 85°C |
- 应用说明英语PDF 1.53 MB R31AN0034EU0102 Rev.1.02 2025年10月21日AI 生成的摘要: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
- 应用说明英语PDF 431 KB 7WDXRDKU4E7E-5-59216 2023年12月06日
- 产品变更通告英语PDF 734 KB 2022年11月16日
- 应用说明英语PDF 256 KB 2021年7月05日AI 生成的摘要: The document explains methods to generate a 1.2V LVCMOS signal from a 1.8V LVCMOS output by attenuating the amplitude without lowering the driver voltage. It details typical LVCMOS driver and receiver configurations, impedance matching using source termination, and the use of a parallel resistor at the receiver input to reduce signal amplitude. Simulation and measurement results demonstrate that adding a parallel resistor effectively lowers the voltage to 1.2V while maintaining signal integrity and minimal impact on jitter and frequency. This approach supports flexible amplitude adjustment for various low-voltage LVCMOS requirements in clock signal applications.
- 应用说明英语PDF 134 KB 2020年6月18日AI 生成的摘要: Various methods to drive crystal input pins or differential receivers are detailed, including direct LVCMOS clock driving with impedance matching via series resistors to prevent signal distortion. The document covers configurations for single-ended HCSL inputs, LVPECL, LVDS, and coaxial inputs, emphasizing proper voltage levels, coupling methods, and termination resistors. It also explains layout considerations for crystal or clock oscillator inputs, load capacitor variations, and level shifting techniques for different voltage domains. Practical component values and connection guidelines ensure signal integrity and compatibility across multiple interface types.
- 应用说明英语PDF 222 KB 2020年5月05日AI 生成的摘要: The document explains the programming procedure for the PhiClock 9FGV100x OTP registers, which include four non-volatile 8-bit registers pre-programmed at the factory. It details two operation modes: I2C mode for register programming and Configuration mode for hardware selection of configurations. The OTP procedure requires applying 6.5V to the OTP_VPP pin and programming registers via I2C. It covers steps for programming four OTP configuration banks and header information, power supply requirements, and timing considerations for successful OTP programming.
- 应用说明英语PDF 486 KB 7WDXRDKU4E7E-5-63374 2018年11月01日
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- 手册 - 软件英语PDF 401 KB 7WDXRDKU4E7E-5-62508 2017年11月27日
手册和指南 (2)
- 应用说明英语PDF 1.53 MB R31AN0034EU0102 Rev.1.02 2025年10月21日AI 生成的摘要: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
- 应用说明英语PDF 431 KB 7WDXRDKU4E7E-5-59216 2023年12月06日
- 应用说明英语PDF 256 KB 2021年7月05日AI 生成的摘要: The document explains methods to generate a 1.2V LVCMOS signal from a 1.8V LVCMOS output by attenuating the amplitude without lowering the driver voltage. It details typical LVCMOS driver and receiver configurations, impedance matching using source termination, and the use of a parallel resistor at the receiver input to reduce signal amplitude. Simulation and measurement results demonstrate that adding a parallel resistor effectively lowers the voltage to 1.2V while maintaining signal integrity and minimal impact on jitter and frequency. This approach supports flexible amplitude adjustment for various low-voltage LVCMOS requirements in clock signal applications.查看更多 (20)
应用说明和白皮书 (20)
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Renesas Boards & Kits
Evaluation Kit for 9FGV1004 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1004 programmable PhiClock™ generator. It provides a convenient way of configuring and programming the blank parts for the 9FGV1004 device. With the onboard USB interface, the Renesas Timing Commander™ Graphical User Interface (GUI) can communicate with... 阅读详情
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Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
This whiteboard video presents a brief overview comparing the evolution of PCI Express data rates through five generations versus that of the common clock jitter specifications.
Renesas's chief PCIe system architect explains how to derive separate reference clock jitter limits from the PCI Express Gen4 and Gen5 specifications.
The IDT PhiClock™ 9FGV100x PCIe Gen 4 clock generators combine space savings, high performance and low power in a single, easy-to-use solution. All PhiClock PCIe reference clock devices integrate crystal load capacitors and offer an optional integrated crystal to simplify designs and save board space. When configured with HCSL outputs for PCIe applications, PhiClock products integrate the output termination resistors, further reducing board space. Extremely small 3 x 3 mm and 4 x 4 mm packages complement the integration for maximum space savings. The programmable PhiClock clock generators combine outstanding PCIe Gen4 performance and outstanding Ethernet performance with phase jitter as low as 225fs rms at 156.25MHz (12k-20M). Extremely low power consumption (as low as 100 mW at 1.8V) allows placement closer to high-power components, which also reduces board space requirements.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
An overview of IDT's full-featured PCI Express (PCIe) clock generators addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
