封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SSOP |
| Pkg. Code: | PVG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 18.4 x 7.5 x 2.3 |
| Pitch (mm): | 0.64 |
环境和出口类别
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | SSOP |
| Lead Count (#) | 56 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| App Jitter Compliance | PCIe Gen1 |
| C-C Jitter Max P-P (ps) | 85 |
| Chipset Manufacturer | Intel |
| Clock Spec. | CK505 Derivative |
| Core Voltage (V) | 3.3 |
| Die Form | No |
| Diff. Output Signaling | HCSL |
| Freq. Accuracy Init. (± PPM) | 100 |
| Function | Clock Generator |
| Input Freq (MHz) | 14.32 - 14.32 |
| Length (mm) | 18.4 |
| MOQ | 208 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Freq Range (MHz) | 14.32 - 400 |
| Output Skew (ps) | 100 |
| Output Voltage (V) | 3.3V, 0.7V |
| Outputs (#) | 19 |
| PCIe Generation | Gen1 |
| Package Area (mm²) | 138 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.64 |
| Pkg. Dimensions (mm) | 18.4 x 7.5 x 2.3 |
| Qty. per Carrier (#) | 26 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 1.05 - 3.3 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 2.3 |
| Width (mm) | 7.5 |
| Xtal Freq (MHz) | 14.32 - 14.32 |
| Xtal Inputs (#) | 1 |
| 已发布 | No |
有关 9LPRS502 的资源
描述
IDT9LPRS502 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. IDT9LPRS502 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.