封装信息
| Lead Count (#) | 72 |
| Pkg. Code | NLG72 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
产品属性
| Lead Count (#) | 72 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Country of Assembly | Taiwan |
| Country of Wafer Fabrication | Taiwan |
| Price (USD) | 1ku | 3.78258 |
| Accepts Spread Spec Input | Yes |
| Advanced Features | Multiple SMBus addresses |
| App Jitter Compliance | 25G EDR, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, DB2000Q, QPI, UPI |
| Architecture | Common, SRIS, SRNS |
| C-C Jitter Max P-P (ps) | 50 |
| Chipset Manufacturer | Intel |
| Clock Spec. | DB2000Q |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 1 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 20 |
| Diff. Termination Resistors | 24 |
| Feedback Input | No |
| Function | Fanout Buffer |
| Input Freq (MHz) | 1 - 400 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Lead Compliant | No |
| Length (mm) | 10 |
| MOQ | 168 |
| Output Banks (#) | 1 |
| Output Enable (OE) Pins | 8 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.7 |
| Outputs (#) | 20 |
| PLL | No |
| Package Area (mm²) | 81.0 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 594 |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
有关 9QXL2000B 的资源
描述
The 9QXL2000B is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen 4 and Gen 5. It offers integrated terminations for 85Ω transmission lines with individual output impedance trim and via SMBus registers.