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2:12 Low-Power PCIe Clock Mux

封装信息

CAD 模型:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

产品属性

Lead Count (#)72
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Country of AssemblyTAIWAN
Country of Wafer FabricationTAIWAN
Accepts Spread Spec InputYes
Additive Phase Jitter Typ RMS (fs)109
Advanced FeaturesMultiple SMBus addresses, HW PLL mode control, SW PLL mode control, Programmable input-to-output skew
App Jitter CompliancePCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI
ArchitectureCommon, SRIS, SRNS
C-C Jitter Max P-P (ps)50
Chipset ManufacturerIntel
Chipset NameC600, Patsburg, Wellsburg, Lewisburg
Clock Spec.DB1200ZL v0.8 Derivative Mux
Core Voltage (V)3.3V
Diff. Input SignalingHCSL
Diff. Inputs2
Diff. Output SignalingLP-HCSL
Diff. Outputs12
Diff. Termination Resistors24
Feedback InputNo
FunctionMultiplexer
Input Freq (MHz)33 - 150
Input TypeHCSL
Inputs (#)2
Length (mm)10
MOQ2500
Output Banks (#)1
Output Enable (OE) Pins12
Output Freq Range (MHz)1 - 400
Output Impedance33
Output Skew (ps)50
Output TypeLP-HCSL
Output Voltage (V)0.7V
Outputs (#)12
PLLYes
Package Area (mm²)100
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeVFQFPN
Power Consumption Typ (mW)482
Prog. ClockYes
Prog. InterfaceSMBUS
Reel Size (in)13
Reference OutputNo
Spread SpectrumYes
Supply Voltage (V)3.3 - 3.3
Tape & ReelYes
Thickness (mm)1
Width (mm)10
已发布No

描述

The 9ZML1232E is a second-generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backward compatible with the 9ZML1232B. The device utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI Express Gen 1-4 or QPI/UPI applications, and provides two configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.