瑞萨电子 (Renesas Electronics Corporation)
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9ZML1252E

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2:12 Low-Power PCIe Clock Mux

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特性

  • 2 configurable low-drift I2O delays up to 2.9ns; maintain transport delay for various topologies
  • LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Separate VDDIO for outputs; allows maximum power savings
  • PLL or Bypass Mode; PLL can de-jitter incoming clock
  • Hardware or software-selectable PLL BW; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • SMBus interface; software can modify device settings without hardware changes
  • 10mm x 10mm 72-QFN package; small board footprint
查找处理器时钟缓冲器的其他产品
9ZML1252E - Block Diagram
9ZML1252E - Pinout
9ZML1252E - Block Diagram
9ZML1252E - Pinout

描述

The 9ZML1252E is a second-generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backward compatible with the 9ZML1232B. The device utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI Express Gen 1-4 or QPI/UPI applications, and provides two configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.

产品参数

属性 值
Chipset Manufacturer Intel
Clock Spec. DB1200ZL v0.8 Derivative Mux
Diff. Outputs 12
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 12
Output Freq Range (MHz) -
Diff. Inputs 2
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 482
Advanced Features Multiple SMBus addresses, HW PLL mode control, SW PLL mode control, Programmable input-to-output skew
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI
Package Area (mm²) 100

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 10.0 x 10.0 x 1.0 72 0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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