瑞萨电子 (Renesas Electronics Corporation)
搜索

9ZXL0632E

有效

6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

立即订购

特性

  • SMBus write lock feature; increases system security
  • PCIe Gen 1–5 compliance
  • LP-HCSL outputs; eliminate 12 resistors, save 20mm² of area
  • 6 OE# pins; hardware control of each output
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL Mode; UPI support
  • 5mm× 5 mm 40-VFQFPN package; small board footprint
查找处理器时钟缓冲器的其他产品
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL0632E - Pinout
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL0632E - Pinout

描述

The 9ZXL0632E is a second-generation, enhanced-performance DB800ZL differential buffer. The part is functionally compatible with the 9ZXL0632A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0632E has an SMBus Write Lockout pin for increased device and system security.

产品参数

属性 值
Chipset Manufacturer Intel
Clock Spec. DB800ZL v1.2 Derivative
Diff. Outputs 6
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 6
Output Freq Range (MHz) 1 - 400
Diff. Inputs 1
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 257
Advanced Features Multiple SMBus addresses, HW PLL mode control, SW PLL mode control, SMBus security
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI, PCIe Gen5, DB2000Q
Package Area (mm²) 81

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 5.0 x 5.0 x 0.9 40 0.4

应用

  • Servers/High-performance Computing
  • nVME Storage
  • Networking
  • Accelerators
  • Industrial Control

当前筛选条件

加载中
加载中

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

加载中 加载中