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9ZXL1951D

有效

19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

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特性

  • LP-HCSL outputs with 85Ω Zout; eliminates 76 termination resistors, saves 130mm² area
  • PCIe Gen 1–5 compliance
  • 8 OE# pins configurable to control up to 16 outputs; easy power management
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL mode; UPI support
  • DIF input and DIF outputs on outer row of pins; easy board routing
  • 6 x 6 mm dual-row 80-GQFN; smallest 19-output Z-buffer
查找处理器时钟缓冲器的其他产品
9ZXL15x0D-19xxD - Block Diagram
9ZXL1951D - Pinout
9ZXL15x0D-19xxD - Block Diagram
9ZXL1951D - Pinout

描述

The 9ZXL1951D is a second-generation, enhanced performance DB1900ZL derivative buffer. The part is a pin-compatible upgrade to the 9ZXL1951A, offering a much improved phase jitter performance. It has 8 OE# pins that can be configured via SMBus to control up to 16 of the device's 19 outputs, and is packaged in a 6 x 6 mm QFN package for maximum space savings. A fixed external feedback maintains low drift for critical QPI/UPI applications.

产品参数

属性 值
Chipset Manufacturer Intel
Clock Spec. DB1900Z v1.7 Derivative
Diff. Outputs 19
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 8
Output Freq Range (MHz) -
Diff. Inputs 1
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 712
Advanced Features Multiple SMBus addresses
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, DB2000Q, PCIe Gen5, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI, PCIe Gen5, DB2000Q
Package Area (mm²) 100

封装选项

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 6.0 x 6.0 x 0.85 80 0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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