概览
描述
The ADC1213D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates up to 105 Msps. Pipelined architecture and output error correction ensure the ADC1213D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it can output data in serial mode, because of the two lanes of differential outputs, which are compliant with the JESD204A standard.
特性
- 2 configurable serial outputs
- Compliant with JESD204A serial transmission standard
- Dual channel 12-bit pipelined ADC core
- High IF capability
- Input bandwidth, 600 MHz
- Power-down and Sleep modes
- Sample rate up to 105 Msps
- SPI interface
产品对比
应用
设计和开发
开发板与套件
演示
ADC1213D105W1 Demo board With FPGA
IDT's ADC demoboard is suitable for dynamic performance evaluations from low to high IF configuration. The FPGA eases the evaluation and analysis of the ADC dynamic and enables use of the full JESD204A feature set.
演示
ADC1213D105WO demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors
Our ADC demonstration board is suitable for dynamic performances evaluation from low to high IF configuration. A FPGA mother board (Xilinx, Altera, and Lattice) could be connected to ease the evaluation and analysis of the ADC dynamic and enable usage of the JESD204A full features sets
模型
ECAD 模块
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