特性
- 14-bit pipelined ADC core
- CMOS or LVDS DDR digital outputs
- Duty cycle stabilizer
- Fast OTR detection
- Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine
- gain
- INL ±
- 1 LSB, DNL ±
- 0.5 LSB (typical)
- Input bandwidth, 600 MHz
- Integrated input buffer
- Offset binary, 2's complement, gray code
- Pin compatible with the ADC1410S065/080/105/125
- Power dissipation, 587 mW at 80 Msps, including analog input buffer
- Power-down and Sleep modes
- Sample rate up to 125 Msps
- SNR, 73 dB / SFDR, 90 dBc
- SPI Interface
ADC1415S125HN - Block Diagram
描述
The ADC1415S125HN is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1415S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1415S supports the LVDS (Low Voltage Differential Signaling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC.
