特性
- Single 2.5V - 3.6V Supply
- Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 and 3
- Supports Dual and Quad Output Read
- 104MHz Maximum Operating Frequency
- Clock-to-Output (tV) of 6ns
- Flexible, Optimized Erase Architecture for Code + Data Storage Applications
- Uniform 4-Kbyte Block Erase
- Uniform 32-Kbyte Block Erase
- Uniform 64-Kbyte Block Erase
- Full Chip Erase
- Hardware Controlled Locking of Protected Blocks via WP Pin
- 3 Protected Programmable Security Register Pages
- Flexible Programming
- Byte/Page Program (1 to 256 Bytes)
- Fast Program and Erase Times
- 0.7ms Typical Page Program (256 Bytes) Time
- 70ms Typical 4-Kbyte Block Erase Time
- 300ms Typical 32-Kbyte Block Erase Time
- 600ms Typical 64-Kbyte Block Erase Time
- JEDEC Standard Manufacturer and Device ID Read Methodology
- Low Power Dissipation
- 2μA Deep Power-Down Current (Typical)
- 10μA Standby current (Typical)
- 4mA Active Read Current (Typical)
- Endurance: 100,000 Program/Erase Cycles
- Data Retention: 20 Years
- Complies with Full Industrial Temperature Range
- Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
- 8-lead SOIC (150-mil and 208-mil)
- 8-pad Ultra-Thin DFN (5mm x 6mm x 0.6mm)
- Die in Wafer Form
描述
The AT25SF321 serial interface Flash memory device is designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF321 is ideal for data storage as well, eliminating the need for additional data storage devices.
The erase block sizes of the AT25SF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register pages can be individually locked.
| Part Number | Status | Samples | Stock | Package | Carrier Type |
|---|---|---|---|---|---|
| AT25SF321-MHD-T | Obsolete | N/A | Out of Stock | DFN | Tape & Reel |
| AT25SF321-MHD-Y | Obsolete | N/A | Out of Stock | UDFN 8MA1 8 - 5x6 | |
| AT25SF321-SHD-B | Obsolete | N/A | Out of Stock | SOIC-W | Tube |
| AT25SF321-SHD-T | Obsolete | N/A | Out of Stock | SOIC-W | Tape & Reel |
| AT25SF321-SSHD-B | Obsolete | N/A | Out of Stock | SOIC-N | Tube |
| AT25SF321-SSHD-T | Obsolete | N/A | Out of Stock | SOIC-N | Tape & Reel |
- 应用说明英语PDF 884 KB R10AN0038EU0100 Rev.1.00 2026年3月10日This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- 应用说明英语PDF 695 KB AN503 2025年9月05日Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- 应用说明英语PDF 2.62 MB AN500 2024年2月13日AI 生成的摘要: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- 应用说明英语PDF 710 KB AN502 2024年1月24日AI 生成的摘要: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
- 指南英语PDF 790 KB SPI_NOR_Flash_Product_Guide_PBFLASH03102022rev-C 2023年6月16日
- 其他英语PDF 1 MB R10DS0315EU0000 Rev.0.00 2022年6月28日
- 应用说明英语PDF 794 KB 2022年5月12日AI 生成的摘要: Renesas NOR flash devices implement multiple protection methods to safeguard memory arrays, status registers, flash states, and resets from accidental or intentional modifications. Protection types include hardware-based write protection via the WP pin and software-based protection through commands controlling status registers and memory blocks. Memory array protection schemes include individual block protection, allowing sector-level lock/unlock, and memory edge protection, which protects contiguous regions aligned to memory edges. Status register protection indirectly secures memory by blocking changes to protection states. Detailed command sets and register bits configure these protections, ensuring robust flash memory integrity.
- 应用说明英语PDF 663 KB 2021年10月18日AI 生成的摘要: Proper power-up and power-down sequencing is critical for NOR Flash memory operation to ensure reliable system performance. The power supply voltage must ramp up monotonically without dips, reaching the minimum operational voltage within specified timing to avoid corrupted initialization. Reset methods, including hardware and JEDEC resets, help ensure the device starts from a known state. Brown-out conditions and power cycling require careful handling to prevent data corruption and ensure stable operation. The document covers power sequencing, reset types, brown-out recovery, power-down, and power-saving modes, providing essential guidelines for system engineers and application developers.
- 应用说明英语PDF 313 KB 2020年7月17日AI 生成的摘要: PCB design for Adesto memory devices requires careful placement of decoupling capacitors close to VCC and GND pins to minimize voltage fluctuations caused by parasitic inductance and capacitance in PCB traces. Proper capacitor selection and placement reduce signal integrity issues, EMI, and noise. Design guidelines vary by package type (SOIC, UDFN, WLCSP, BGA) and PCB layer count. Signal routing rules ensure reliable data and control signals. Special cases include parallel devices, reset signal handling, and test point integration. The document provides detailed layout recommendations for each package type to optimize device performance and reliability.
- 产品变更通告英语PDF 528 KB 2020年6月26日
推荐文档 (1)
数据手册 (1)
- 指南英语PDF 790 KB SPI_NOR_Flash_Product_Guide_PBFLASH03102022rev-C 2023年6月16日
手册和指南 (1)
- 应用说明英语PDF 884 KB R10AN0038EU0100 Rev.1.00 2026年3月10日This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- 应用说明英语PDF 695 KB AN503 2025年9月05日Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- 应用说明英语PDF 2.62 MB AN500 2024年2月13日AI 生成的摘要: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- 应用说明英语PDF 710 KB AN502 2024年1月24日AI 生成的摘要: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
应用说明和白皮书 (8)
- 产品变更通告英语PDF 528 KB 2020年6月26日
产品通告(产品变更、EOL 等) (3)
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
营销资料 (1)
- 其他英语PDF 1 MB R10DS0315EU0000 Rev.0.00 2022年6月28日
其他 (4)
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
筛选
当前筛选条件
软件与工具
按类型筛选
按供应商筛选
样例程序
按应用筛选
按功能筛选
按编译器筛选
按 IDE 筛选
模拟模型
Partner Solutions
- Development Tool中文µISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).提供方: Algocraft Srl
- Development Tool中文WriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a ...提供方: Algocraft Srl
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
No Results Found.
确保所有关键词拼写正确。
尝试使用更少、不同或更宽泛的词语来改变搜索结果。
如果您使用了筛选器,请考虑取消选择某些筛选器选项以扩大搜索结果。
- 搜索我们丰富的知识库,帮助您解答常见问题
- 前往支持论坛,获取瑞萨电子技术专家和社群的帮助
- Development Tool中文µISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).提供方: Algocraft Srl
- Development Tool中文WriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a ...提供方: Algocraft Srl