封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | CFP |
| Pkg. Code: | KBG |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 10.41 x 6.86 x 0.00 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | CFP |
| Lead Count (#) | 16 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| DLA SMD | 5962R9662901VXC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| DSEE (MeV·cm2/mg) | 75 |
| Length (mm) | 10.4 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 10.4 x 6.9 x 0.00 |
| Qualification Level | QML Class V (space) |
| Rating | Space |
| TID HDR (krad(Si)) | 100 |
| TID LDR (krad(Si)) | ELDRS free |
| Width (mm) | 6.9 |
有关 CD4027BMS 的资源
描述
The CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D-Type flip-flop. The CD4027BMS is useful in performing control, register and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high-level signal is present at either the Set or Reset input. The CD4027BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1E and Ceramic Flatpack H6W.