封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | SBDIP |
| Pkg. Code: | DAV |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 20.32 x 7.49 x 2.41 |
| Pitch (mm): | 2.54 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | |
| HTS (US) |
产品属性
| Pkg. Type | SBDIP |
| Lead Count (#) | 16 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pitch (mm) | 2.5 |
| Pkg. Dimensions (mm) | 20.3 x 7.5 x 2.41 |
| DLA SMD | 5962R9663401VEC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| DSEE (MeV·cm2/mg) | 75 |
| Length (mm) | 20.3 |
| Qualification Level | QML Class V (space) |
| Rating | Space |
| TID HDR (krad(Si)) | 100 |
| TID LDR (krad(Si)) | ELDRS free |
| Thickness (mm) | 2.41 |
| Width (mm) | 7.5 |
有关 CD4043BMS 的资源
描述
The CD4043BMS devices are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS devices are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual Set and Reset inputs. The Q outputs are controlled by a common Enable input. A logic 1 or high on the Enable input connects the latch states to the Q outputs. A logic 0 or low on the Enable input disconnects the latch states from the Q outputs; this results in an open circuit feature allowing for common busing of the outputs. The CD4043BMS and CD4044BMS are supplied in these 16- lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1C (CD4043BMS) and HIE (CD4044BMS), and Ceramic Flatpack H3X (CD4043BMS) and H6W (CD4044BMS).