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概览

描述

The evaluation kit supports electrical AC and DC measurements of the 8V19N850DNLGI, a fully integrated radio synchronizer and JESD204B/C clock jitter attenuator. The device on the board accepts any input frequency from 1Hz to 1GHz. Locked to a selected input, the device PLLs generate clock and SYSREF signals for converter reference frequency and data frame synchronization. The 8V19N850 supports two independent frequency domains: One generates transport network clocks, such as Ethernet frequencies at 4 outputs, and the other one generates radio base station clocks at 12 outputs (ADC/DAC reference clocks and SYSREF signals). Each frequency domain uses a Digital PLL (DPLL) for frequency translation, clock filtering, and jitter attenuation. The DPLLs provide a programmable bandwidth and a Digitally Controlled Oscillator (DCO) function for real-time frequency/phase adjustment.

特性

  • Board has SMA connectors to the relevant I/O of the device
    • 2 differential clock inputs
    • 4 differential digital outputs
    • 5 differential RF-PLL outputs
    • 5 SYSREF outputs (JESD204B/C)
    • Onboard EEPROM stores startup-configuration data
    • 4 GPIO controls
    • Selectable output buffer voltage
    • XO_DPLL and OSCI terminals can use a laboratory signal generator or OCXO/TCXO/XO components and a board
    • Laboratory power supply connectors
    • Serial port for configuration and register readout

应用

文档

类型 文档标题 日期
手册 - 开发工具 PDF 2.66 MB
指南 PDF 600 KB
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设计和开发

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