概览
描述
3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer. With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions.
特性
• Phase-Lock Loop Clock Distribution for Synchronous DRAM applications
• Distributes one clock input to one bank of ten outputs
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
