封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PAG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 14.0 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
产品属性
| Pkg. Type | TSSOP |
| Lead Count (#) | 56 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Advanced Features | Programmable Clock, Spread Spectrum |
| App Jitter Compliance | PCIe Gen1, FBDIMM |
| C-C Jitter Max P-P (ps) | 50 |
| Chipset Manufacturer | Intel |
| Chipset Name | DB1200G |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 133 - 133, 160 - 160, 167 - 167, 200 - 200, 267 - 267, 333 - 333, 400 - 400 |
| Input Type | HCSL |
| Inputs (#) | 1 |
| Length (mm) | 14 |
| MOQ | 612 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 133 - 133, 160 - 160, 167 - 167, 200 - 200, 267 - 267, 320 - 320, 333 - 333 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 12 |
| Package Area (mm²) | 85.4 |
| Pb Free Category | e3 Sn |
| Phase Jitter Max RMS (ps) | 100 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 14.0 x 6.1 x 1.0 |
| Prog. Clock | Yes |
| Prog. Interface | SMBUS |
| Qty. per Carrier (#) | 34 |
| Qty. per Reel (#) | 0 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
| 已发布 | No |
有关 CV128 的资源
描述
The CV128 differential buffer complies with Intel DB1200G rev. 0.5, and is designed to work in conjunction with the main clock of CK409, CK410/CK410M and CK410B etc., PLL is off in bypass mode and no clock detect.