特性
- Throughput Rate 130MSPS
- Low Power (at 100MSPS) at 5V 175mW, at 3V 32mW
- Adjustable Full Scale Output Current 2mA to 20mA
- Internal 1.2V Bandgap Voltage Reference
- Single Power Supply from +5V to +3V
- Power Down Mode
- CMOS Compatible Inputs
- Excellent Spurious Free Dynamic Range (77dBc, fS = 50MSPS, fOUT = 2.51MHz)
- Excellent Multitone Intermodulation Distortion
- Pb-Free Available (RoHS Compliant)
描述
The HI5960 is a 14-bit, 130MSPS (Mega Samples Per Second), High-Speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. This device complements the CommLink HI5x60 and HI5x28 family of High-Speed converters, which includes 8, 10, 12, and 14-bit devices.
应用
- Cellular Basestations
- WLL, Basestation and Subscriber Units
- Medical/Test Instrumentation
- Wireless Communications Systems
- Direct Digital Frequency Synthesis
- High Resolution Imaging Systems
- Arbitrary Waveform Generators
| Part Number | Status | Samples | Stock | RoHS | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pitch (mm) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HI5960IAZ | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 28# | Tube | 0.7mm | 9.7 x 4.4 x 0.00 | No | -40 to +85°C | ||
| HI5960IAZ-T | Obsolete | N/A | Out of Stock | RoHS:EN | TSSOP | 28# | Reel | 0.7mm | 9.7 x 4.4 x 0.00 | No | -40 to +85°C | ||
| HI5960IBZ | Obsolete | N/A | Out of Stock | RoHS:EN | SOICW | 28# | Tube | 3 | 1.3mm | 17.9 x 7.5 x 0.20 | Yes | Pb-Free 100% Matte Tin Plate w/Anneal-e3 | -40 to +85°C |
- 其他英语PDF 234 KB hi5828_isl5217wedge 2017年11月18日
- 产品变更通告英语PDF 98 KB PCN12094 2012年12月19日
- 应用说明英语PDF 503 KB an9675 1999年8月13日AI 生成的摘要: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- 应用说明英语PDF 1.08 MB an002 1998年11月19日AI 生成的摘要: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- 应用说明英语PDF 287 KB an9705 1997年2月21日AI 生成的摘要: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
推荐文档 (1)
数据手册 (1)
手册和指南 (1)
- 应用说明英语PDF 503 KB an9675 1999年8月13日AI 生成的摘要: Effective Number of Bits (ENOB) depends critically on precise coherence in A/D sampling, with small frequency shifts significantly impacting accuracy. Unwrapping reconstructs coherently sampled sine waves, while windowing controls spectral leakage by shaping the acquisition window. Resampling and interpolation adjust sample sets to avoid leakage in FFT analysis. Different window functions balance side lobe levels and bandwidth, affecting spectral resolution and leakage reduction.
- 应用说明英语PDF 1.08 MB an002 1998年11月19日AI 生成的摘要: Data acquisition and conversion involve quantization, where the smallest resolvable analog difference (quantum) depends on the full scale range and resolution. Quantization introduces an irreducible error called quantizing error or noise. Aperture time, the conversion time uncertainty, causes amplitude errors when signals change during conversion. Sample-hold circuits reduce aperture time by storing sampled signals. The Sampling Theorem states that sampling frequency must be at least twice the highest signal frequency to avoid distortion from frequency folding or aliasing. Natural binary code is commonly used for digital representation in converters, with the most and least significant bits defining the code's resolution and value.
- 应用说明英语PDF 287 KB an9705 1997年2月21日AI 生成的摘要: Coherent sampling requires the ratio of signal frequency to sampling frequency to be a rational number, expressed as ko/N. When this condition is not met, frequency smearing occurs across bins. Data Acquisition Systems (DAS) can mitigate this by windowing, fixing sampling frequency and tuning input frequency, or fixing input frequency and tuning sampling frequency. The latter two methods are practical for most systems. Pseudo-code illustrates the frequency response for non-integer ko values.
应用说明和白皮书 (3)
- 产品变更通告英语PDF 98 KB PCN12094 2012年12月19日
产品通告(产品变更、EOL 等) (2)
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营销资料 (1)
- 其他英语PDF 234 KB hi5828_isl5217wedge 2017年11月18日
其他 (2)
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Renesas Boards & Kits
14-Bit, 130MSPS, High-Speed D/A Converter Evaluation Board
The HI5960SOICEVAL1 evaluation board provides a quick and easy method for evaluating the HI5960 14-bit, 130MSPS high-speed digital-to-analog converters (DACs). The board is configured so that the converter outputs differential current into a transformer circuit to form an output voltage. The... 阅读详情