特性
- Input Sample Rates to 52MSPS
- Internal AGC Loop for Output Level Stability
- Parallel or Serial Output Data Formats
- 10-Bit Real or Complex Inputs
- Bidirectional 8-Bit Microprocessor Interface
- Frequency Selectivity 0.013Hz
- Low Pass Filter Configurable as Three Stage Cascaded- Integrator-Comb (CIC), Integrate and Dump, or Bypass
- Fixed Decimation from 1-4096, or Adjusted by NCO Synchronization with Baseband Waveforms
- Input Level Detection for External IF AGC Loop
- Designed to Operate with HSP50210 Digital Costas Loop
- 84 Lead PLCC
描述
Support is limited to customers who have already adopted these products.
The Digital Quadrature Tuner (DQT) provides many of the functions required for digital demodulation. These functions include carrier LO generation and mixing, baseband sampling, programmable bandwidth filtering, baseband AGC, and IF AGC error detection. Serial control inputs are provided which can be used to interface with external symbol and carrier tracking loops. These elements make the DQT ideal for demodulator applications with multiple operational modes or data rates. The DQT may be used with HSP50210 Digital Costas Loop to function as a demodulator for BPSK, QPSK, 8-PSK OQPSK, FSK, FM, and AM signals. The DQT processes a real or complex input digitized at rates up to 52 MSPS. The channel of interest is shifted to DC by a complex multiplication with the internal LO. The quadrature LO is generated by a numerically controlled oscillator (NCO) with a tuning resolution of 0. 012Hz at a 52MHz sample rate. The output of the complex multiplier is gain corrected and fed into identical low pass FIR filters. Each filter is comprised of a decimating low pass filter followed by an optional compensation filter. The decimating low pass filter is a 3 stage Cascaded-Integrator-Comb (CIC) filter. The CIC filter can be configured as an integrate and dump filter or a third order CIC filter with a (sin(X)/X)3 response. Compensation filters are provided to flatten the (sin(X)/X)N response of the CIC. If none of the filtering options are desired, they may be bypassed. The filter bandwidth is set by the decimation rate of the CIC filter. The decimation rate may be fixed or adjusted dynamically by a symbol tracking loop to synchronize the output samples to symbol boundaries. The decimation rate may range from 1-4096. An internal AGC loop is provided to maintain the output magnitude at a desired level. Also, an input level detector can be used to supply error signal for an external IF AGC loop closed around the A/D. The DQT output is provided in either serial or parallel formats to support interfacing with a variety DSP processors or digital filter components. This device is configurable over a general purpose 8-bit parallel bidirectional microprocessor control bus.
应用
- Satellite Receivers and Modems
- Complex Upconversion/Modulation
- Tuner for Digital Demodulators
- Digital PLLs
- Related Products: HSP50210 Digital Costas Loop; A/D Products HI5703, HI5746, HI5766
- HSP50110/210EVAL Digital Demod Evaluation Board
| Part Number | Status | Samples | Stock | Package | Carrier Type | MOQ |
|---|---|---|---|---|---|---|
| HSP50110JC-52 | Obsolete | N/A | In Stock | PLCC | Tube | 45 |
| HSP50110JC-52Z | Obsolete | N/A | In Stock | PLCC | Tube | 45 |
| HSP50110JI-52 | Obsolete | N/A | In Stock | PLCC | Tube | 30 |
| HSP50110JI-52Z | Obsolete | N/A | Out of Stock | PLCC | Tube | 60 |
- EOL 通告英语PDF 226 KB PLC16037 2016年4月12日
- 应用说明英语PDF 192 KB an9715 2002年1月10日AI 生成的摘要: The document provides operational tips for the HSP50110/210EVAL board, focusing on setting the DQT output rate relative to the baud rate, typically twice the baud rate depending on filter types. It explains using the NCOM evaluation board as a modulator, including carrier frequency configuration and the necessity of running NCOM and demodulation software simultaneously. External filtering after the D/A converter is recommended to maintain signal quality, and output amplitude can be finely adjusted. The HI5721EV D/A board is compatible for generating analog modulated IF signals. The document also includes important legal disclaimers and contact information for Renesas Electronics worldwide.
- 应用说明英语PDF 232 KB an9658 2000年5月08日AI 生成的摘要: The document details the implementation of a high-rate radio receiver using specific Renesas components. It emphasizes the importance of anti-aliasing filters to prevent signal interference and aliasing during analog-to-digital conversion. The design includes oversampling and decimation techniques, matched baseband filters, and digital signal processing elements like the Digital Quadrature Tuner and Costas loop. The system limits symbol rates to 22.5MHz and uses level detection to optimize input signal levels.
- 应用说明英语PDF 356 KB an9676 2000年5月01日AI 生成的摘要: The document explains loading custom digital filters into the HSP50110/210 evaluation board using SERINADE software. It details creating and modifying filter coefficient files with a specific header format, importing these files into SERINADE, and generating report files (*.RPT) for programming the evaluation board. The process includes setting parameters such as FIR type, decimation factors, and filter paths. It also discusses the frequency response of Root Raised Cosine (RRC) filters, their tolerance to mismatches, and how to configure the evaluation software to load the custom filters.
- 应用说明英语PDF 328 KB an9661 2000年5月01日AI 生成的摘要: The document explains implementing polyphase filtering using the HSP50110, HSP50210, and HSP43168 devices. It details clock and control connections, emphasizing the programmable divider and resampler NCO for precise phase resolution. The SSTRB signal synchronizes sample phases with the DATARDY signal. It describes the FIR filter's role in resampling and decimation, highlighting the dual FIR filter's capability to handle I and Q components with up to 256 taps. The document also covers synchronization of signals and jitter considerations in the NCO output.
- 应用说明英语PDF 375 KB an9657 2000年4月29日AI 生成的摘要: The document explains various binary code formats used in data conversion, including Offset Binary, 1's Complement, 2's Complement, and Sign Magnitude. It illustrates these formats by plotting cosine waveforms digitally. Additionally, it provides important legal and usage notices from Renesas Electronics, covering product liability, warranty disclaimers, quality grades, safety responsibilities, environmental compliance, and export control regulations. Contact information for global Renesas sales offices is also included.
- 应用说明英语PDF 200 KB an9660 1999年3月12日AI 生成的摘要: The document details various output signals and control buses used in signal processing applications, including integration counters, two's complement outputs, and interfaces for FEC decoders. It highlights signals useful for fault detection, AGC monitoring, signal detection, and lock detection. The notice section outlines legal disclaimers, product quality grades, usage restrictions, and safety responsibilities related to Renesas Electronics products.
- 其他英语PDF 239 KB tb311 1998年8月11日
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- 应用说明英语PDF 192 KB an9715 2002年1月10日AI 生成的摘要: The document provides operational tips for the HSP50110/210EVAL board, focusing on setting the DQT output rate relative to the baud rate, typically twice the baud rate depending on filter types. It explains using the NCOM evaluation board as a modulator, including carrier frequency configuration and the necessity of running NCOM and demodulation software simultaneously. External filtering after the D/A converter is recommended to maintain signal quality, and output amplitude can be finely adjusted. The HI5721EV D/A board is compatible for generating analog modulated IF signals. The document also includes important legal disclaimers and contact information for Renesas Electronics worldwide.
- 应用说明英语PDF 232 KB an9658 2000年5月08日AI 生成的摘要: The document details the implementation of a high-rate radio receiver using specific Renesas components. It emphasizes the importance of anti-aliasing filters to prevent signal interference and aliasing during analog-to-digital conversion. The design includes oversampling and decimation techniques, matched baseband filters, and digital signal processing elements like the Digital Quadrature Tuner and Costas loop. The system limits symbol rates to 22.5MHz and uses level detection to optimize input signal levels.
- 应用说明英语PDF 356 KB an9676 2000年5月01日AI 生成的摘要: The document explains loading custom digital filters into the HSP50110/210 evaluation board using SERINADE software. It details creating and modifying filter coefficient files with a specific header format, importing these files into SERINADE, and generating report files (*.RPT) for programming the evaluation board. The process includes setting parameters such as FIR type, decimation factors, and filter paths. It also discusses the frequency response of Root Raised Cosine (RRC) filters, their tolerance to mismatches, and how to configure the evaluation software to load the custom filters.
- 应用说明英语PDF 328 KB an9661 2000年5月01日AI 生成的摘要: The document explains implementing polyphase filtering using the HSP50110, HSP50210, and HSP43168 devices. It details clock and control connections, emphasizing the programmable divider and resampler NCO for precise phase resolution. The SSTRB signal synchronizes sample phases with the DATARDY signal. It describes the FIR filter's role in resampling and decimation, highlighting the dual FIR filter's capability to handle I and Q components with up to 256 taps. The document also covers synchronization of signals and jitter considerations in the NCO output.
- 应用说明英语PDF 375 KB an9657 2000年4月29日AI 生成的摘要: The document explains various binary code formats used in data conversion, including Offset Binary, 1's Complement, 2's Complement, and Sign Magnitude. It illustrates these formats by plotting cosine waveforms digitally. Additionally, it provides important legal and usage notices from Renesas Electronics, covering product liability, warranty disclaimers, quality grades, safety responsibilities, environmental compliance, and export control regulations. Contact information for global Renesas sales offices is also included.查看更多 (6)
应用说明和白皮书 (6)
- EOL 通告英语PDF 226 KB PLC16037 2016年4月12日
产品通告(产品变更、EOL 等) (1)
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