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Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch

封装信息

CAD 模型:View CAD Model
Pkg. Type:TQFN
Pkg. Code:LFC
Lead Count (#):16
Pkg. Dimensions (mm):3.0 x 3.0 x 0.80
Pitch (mm):0.5

环境和出口类别

Moisture Sensitivity Level (MSL)2
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
RoHS (ISL84467IRTZ-T)下载

产品属性

Lead Count (#)16
Carrier TypeReel
Moisture Sensitivity Level (MSL)2
Pitch (mm)0.5
Pkg. Dimensions (mm)3.0 x 3.0 x 0.80
Pb (Lead) FreeYes
Pb Free CategoryPb-Free 100% Matte Tin Plate w/Anneal-e3
Temp. Range (°C)-40 to +85°C
Country of AssemblyMALAYSIA
Country of Wafer FabricationTAIWAN
Channels (#)8
Charge Injection (pC)248
Configuration4 x 2:1
Drain Capacitance102
IS (mA)0.00015
Leakage (nA)70
Length (mm)3
MOQ6000
Pkg. TypeTQFN
Price (USD)$0.909
Qualification LevelStandard
RDS (ON) (Ohms)0.39
Source Cap (pf)38
Supply Voltage Vcc Range1.65 to 4.5
Switch or MUXSwitch/MUX
TOFF (ns)16
TON (ns)33
Thickness (mm)0.8
Type of SwitchSPDT (Dual DPDT)
VCC (Single) (V)1.65 - 4.5
Width (mm)3

描述

The Intersil ISL84467 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1. 65V to +4. 5V supply. Targeted applications include battery powered equipment that benefit from low rON (0. 39Ω) and fast switching speeds (tON = 33ns, tOFF = 16ns). The digital logic input is 1. 8V logic-compatible when using a single +3V supply. With a supply voltage of 4. 2V and logic high voltage of 2. 85V at both logic inputs, the part draws only 12µA max of ICC current. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to mux-in additional functionality while reducing ASIC design risk. The ISL84467 is offered in small form factor package, alleviating board space limitations. The ISL84467 consists of four SPDT switches. It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each. The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer.