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3.3V Dual LVTTL/LVCMOS-to-Differential LVPECL Translator

封装信息

Pkg. Type:TSSOP
Pkg. Code:DVG8
Lead Count (#):8
Pkg. Dimensions (mm):3.0 x 3.0 x 0.97
Pitch (mm):0.65

环境和出口类别

Pb (Lead) FreeYes
Moisture Sensitivity Level (MSL)3
ECCN (US)
HTS (US)

产品属性

Pkg. TypeTSSOP
Lead Count (#)8
Pb (Lead) FreeYes
Carrier TypeTube
Additive Phase Jitter Typ RMS (fs)250
Additive Phase Jitter Typ RMS (ps)0.25
Core Voltage (V)3.3
FunctionBuffer
Input Freq (MHz)1000
Input TypeLVCMOS
Inputs (#)2
Length (mm)3
MOQ200
Moisture Sensitivity Level (MSL)3
Output Banks (#)2
Output Freq Range (MHz)1000
Output Skew (ps)100
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)2
Package Area (mm²)9
Pb Free Categorye3 Sn
Pitch (mm)0.65
Pkg. Dimensions (mm)3.0 x 3.0 x 0.97
Qty. per Carrier (#)96
Qty. per Reel (#)0
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Temp. Range (°C)0 to 70°C
Thickness (mm)0.97
Width (mm)3
已发布No

描述

The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications.