特性
- Input clock frequency of 1 kHz to 170 MHz
- Output clock frequency of 500 kHz to 160 MHz
- Jitter attenuation of input clock provided by VCXO circuit. Jitter transfer characteristics user configured through selection of external loop filter components.
- 3:1 Input MUX for input reference clocks
- PLL lock status output
- PLL Clear function allows seamless synchronizing to an altered input clock phase, virtually eliminating the generation of wander or extra clock cycles.
- VCXO-based clock generation offers very low jitter and phase noise generation, even with a low frequency or jittery input clock.
- 2nd PLL provides translation of VCXO PLL output (VCLK) to higher or alternate clock frequencies (TCLK).
- Device will free-run in the absence of an input clock based on the VCXO crystal frequency.
- 56 pin TSSOP package
- Single 3.3 V power supply
- 5 V tolerant inputs on ICLK0 and ICLK1
描述
The MK2069-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation, and frequency multiplication or translation. It can accept an unstable, jittery input clock and provide a de-jittered, low phase noise output clock at a user determined frequency. The device's clock multiplication ratios are user selectable since all major PLL divider blocks can be configured through device pin settings. External PLL loop filter components allow tailoring of the VCXO PLL loop response and therefore the clock jitter attenuation characteristics. The MK2069-01 is ideal for line card applications. Its three input MUX enables selection of the master or slave (backup) system clocks, as well as a backup local line card clock. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low.