特性
- Input clock frequency 1 kHz to 170 MHz
- Output clock frequency of 500 kHz to 160 MHz
- Clock translation examples: T1 (1.544 MHz) to/from E1 (2.048 MHz) T3 (44.736 MHz) to/from E3 (34.368 MHz) OC-3 (155.52 MHz) to/from T1 (1.544 MHz) CCIR-601 (27 MHz) to/from SMPTE 274M (74.125 MHz)
- Jitter attenuation of input clock provided by VCXO circuit. Jitter transfer characteristics user configured through external loop filter component selection.
- Low jitter and phase noise generation.
- PLL lock status output
- PLL Clear function allows seamless synchronizing to an altered input clock phase
- 2nd PLL provides frequency translation of VCXO PLL output (VCLK) to a higher or alternate output frequency (TCLK).
- Device will free-run in the absence of an input clock based on VCXO frequency.
- 56-pin TSSOP package
- Single 3.3 V power supply
- 5 V tolerant clock input
- Pb (lead) free package
MK2069-04 - Block Diagram
描述
The MK2069-04 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that features a PLL (Phase-Locked Loop) input reference divider and feedback divider that have a wide numeric range selectable by the user. This enables a complex PLL multiplication ratio that can be used for translation between clock frequency standards. The on-chip VCXO produces a stable, low jitter output clock using a phase detector frequency down to 8 kHz or lower. This means the MK2069-04 can translate between clock frequencies that have a low common denominator, such as the 8 kHz frame clock common with telecom standards. The MK2069-04 also provides jitter attenuation of the input clock and can accept a low input frequency as well. The device is optimized for user configurability by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of user configurability. The MK2069-04 includes a lock detector (LD) output that serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock.
