RC19004

特性

LP-HCSL outputs eliminate up to 16 terminated resistors
PCIe Gen 1–7 compliance
Drive both source-terminated and double-terminated loads
Selectable output slew rate via pin
Support both 85Ω and 100Ω output impedance versions
Open-drain LOS (Loss-Of-Signal) indication output
Power down tolerance (PDT)
Flexible startup sequencing (FSS)
Automatic clock parking (ACP)
Dedicated OE# pins to control group output
4-wire Side-Band interface and device daisy-chaining
SMBus write protection features with 9 selectable addresses
4mm × 4mm 28-VFQFPN package

描述

The RC19004 is a 4-output PCIe Gen7 buffer that is backward compatible with earlier PCIe generations. The RC19004 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.

产品参数

属性	值
Diff. Outputs	4
Diff. Output Signaling	LP-HCSL
Output Freq Range (MHz)	1 - 400
Diff. Inputs	1
Power Consumption Typ (mW)	125, 128
Supply Voltage (V)	3.3 - 3.3
Output Type	LP-HCSL
Battery Backup	No
Battery Seal	No
CPU Supervisory Function POR	No
Crystal Frequency Trimming	No
Frequency Out Pin	No
Inputs (#)	1
Input Freq (MHz)	1 - 400
Adjustable Phase	No
Noise Floor (dBc/Hz)	-154
Channels (#)	2
Additive Phase Jitter Typ RMS (fs)	30
Function	Fanout Buffer
Input Type	LVDS, HCSL
Output Banks (#)	1
Core Voltage (V)	3.3
Output Voltage (V)	0.8