封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
环境和出口类别
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
产品属性
| Lead Count (#) | 72 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| 105°C Max. Case Temp. | 0 |
| Adjustable Phase | Yes |
| Advanced Features | PWM Encoder/Decoder, ToD, 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, T-BC, T-TSC Class C, eEEC |
| Application | Wireless Baseband Unit (BBU), Distributed Unit (DU), Centralized Unit (CU), Radio Unit (RU) |
| Channels (#) | 6 |
| Core Voltage (V) | 2.5V, 3.3V |
| DPLL Channels (#) | 6 |
| Diff. Inputs | 5 |
| Diff. Outputs | 12 |
| Family Name | ClockMatrix |
| Feedback Divider Resolution (bits) | 48 |
| Fractional Output Dividers (#) | 6 |
| Input Freq (MHz) | 0.001 - 1000 |
| Input Redundancy | Input Monitor, Digital holdover, Hitless switch, Phase-slope limiting |
| Input Ref. Divider Resolution (bits) | 4 |
| Input Type | HCSL, LVDS, LVHSTL, LVPECL, SSTL |
| Inputs (#) | 10 |
| JESD204B/C Compliant | Yes |
| Length (mm) | 10 |
| Longevity | 2040 4月 |
| Loop Bandwidth Range (Hz) | 0.0001 - 12000 |
| MOQ | 168 |
| Noise Floor (dBc/Hz) | -158 |
| Output Banks (#) | 6 |
| Output Divider Resolution (bits) | 32 |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Output Skew (ps) | 50 |
| Output Type | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL |
| Output Voltage (V) | 1.2V, 1.5V, 1.8V, 2.5V, 3.3V |
| Outputs (#) | 24 |
| Phase Jitter Typ RMS (ps) | 0.15 |
| Phase Noise Supports GSM | No |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Product Category | FemtoClock NG |
| Prog. Interface | I2C, SPI |
| Reference Output | No |
| Requires Terms and Conditions | Requires acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 3.3 - 3.3, 2.5 - 2.5, 1.8 - 1.8 |
| Synthesis Mode | Fractional, Integer |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
| Xtal Freq (KHz) | 25 - 54 |
| 已发布 | No |
有关 RC32012A 的资源
描述
RC32012A 可再生和分配超低抖动时钟输出，并具有多达 4 个独立频域，这些频域既可以锁定到外部参考时钟，也可以锁定到自由运行晶体或振荡器。 数字 PLL（DPLL）支持在来自冗余时序源的参考信号之间进行无中断信号切换。 该器件支持多个独立的定时通道：IEEE 1588 时钟合成、SyncE 时钟生成、抖动衰减和无线电时钟生成，包括用于转换器的 SYSREF 生成。 所有输入到输入、输入到输出和输出到输出相位偏差均可精确管理。 该器件输出超低抖动时钟，可直接同步运行速率高达 56Gbps 的 SERDES；以及 CPRI/OBSAI、SONET/SDH ADC/DAC。 该器件非常适合用于 100G/200G/400G/800G 电信交换线路卡、交换卡和无线小型蜂窝应用。
如需查看该产品系列中的其他器件，请访问ClockMatrix 定时解决方案页面。