瑞萨电子 (Renesas Electronics Corporation)
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RC32504A

有效
产品长期供货

FemtoClock 2 Jitter Attenuator or Clock Generator

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概览

The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC, or FPGA that requires several reference clocks with a jitter performance of less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.

RC32504A - Block Diagram
RC32504A - Pin Assignment
RC32504A - Block Diagram
RC32504A - Pin Assignment
  • Jitter below 100fs RMS (10kHz to 20MHz)
  • Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
  • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
    • Operates from a 25MHz to 80MHz crystal or XO
    • APLL frequency independent of input/crystal frequency
    • Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO)
    • DPLL loop filter programmable from 0.1Hz to 12kHz
    • DCO has a tuning granularity of < 1ppb
  • Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
    • Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
    • Reference monitor qualifies/disqualifies input clock
  • Programmable status output
  • 4 differential/8 LVCMOS outputs
    • Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
    • Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
    • Differential output swing is selectable: 400mV to 800mV
    • Output clock phase individually adjustable in 100ps steps
    • Output Enable input with programmable effect
  • Supports up to 1MHz I²C or up to 20MHz SPI serial processor port
  • Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
  • 4mm × 4mm 24-VFQFPN package

文档

设计和开发

ECAD 模块

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扩展 ECAD 模块
Diagram of ECAD Models

模型
类型 文档标题 日期
模型 - IBIS
RC32504A IBIS Model
ZIP 28 KB
1 项目
此为出厂可配置设备。试用自定义部件配置工具。

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资源

视频和培训

Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.

新闻和博客

博客
2021年4月27日
Benefits of a Point-of-Use Clock for Jitter Optimization
博客
2019年6月15日
Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility
新闻
2017年12月14日
IDT's Latest Timing Products Deliver Industry-leading Phase Noise for 100G and 400G Applications
新闻
2016年7月18日
New IDT 12-Output Clock Generator Delivers Best-In-Class Jitter Performance for Today’s Demanding Applications