瑞萨电子 (Renesas Electronics Corporation) - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community
搜索

RMQC4A1818DGBA-302

过时

18-Mbit DDR™ II SRAM 2-word Burst

特性

  • Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
  • Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with μs restart
  • I/O Common data input/output bus Pipelined double data rate operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling
  • Function Two-tick burst for low DDR transaction size Internally self-timed write control Simple control logic for easy depth expansion JTAG 1149.1 compatible test access port
  • Package 165 FBGA package (13 x 15 x 1.4 mm)

描述

The RMQC4A1836DGBA is a 524, 288-word by 36-bit and the RMQC4A1818DGBA is a 1, 048, 576-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.

Part NumberStatusSamplesStockRoHSPackageCarrier TypeMoisture Sensitivity Level (MSL)
RMQC4A1818DGBA-302#AC0ObsoleteN/AOut of StockRoHS:EN
RoHS:JA
LBGATray3
加载中

筛选

    推荐文档 (1)

  1. 数据手册
    英语
    RMQC4A1836DGBA, RMQC4A1818DGBA
    RECOMMENDED
    PDF 848 KB R10DS0248EJ0100 Rev.1.00 2015年1月13日

    数据手册 (1)

  1. 数据手册
    英语
    RMQC4A1836DGBA, RMQC4A1818DGBA
    RECOMMENDED
    PDF 848 KB R10DS0248EJ0100 Rev.1.00 2015年1月13日

    产品通告（产品变更、EOL 等） (4)

  1. EOL 通告
    英语
    End Of Life Notice [SAF-B-24-0008]
    PDF 692 KB SAF-B-24-0008 日本語 2024年3月15日
  2. 产品变更通告
    英语
    Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction)
    PDF 4.86 MB PC-WRP-A001C/E 日本語 2018年1月23日
  3. 产品变更通告
    英语
    Unification of a JEDEC tray and a embossed carrier tape for LQFP package ( PC-WRP-A001B/E )
    PDF 3.74 MB PC-WRP-A001B/E 日本語 2017年3月08日
  4. 产品变更通告
    英语
    Unification of a JEDEC tray and a embossed carrier tape for LQFP package ( PC-WRP-A001A/E )
    PDF 1.46 MB PC-WRP-A001A/E 日本語 2016年7月01日
加载中
加载中

筛选

模拟模型

    模拟模型 (4)

  1. 模型 - IBIS
    英语
    RMQC4A1818DGBA-302 BSDL (RMQC4A1818DGBA.BSDL)
    登录后下载 BSDL 13 KB D6003196 日本語 2019年3月27日
  2. 模型 - IBIS
    英语
    RMQC4A1818DGBA-302 Verilog model for NC Verilog (nc_rmqc4a1818.vp)
    登录后下载 VP 115 KB D6003392 日本語 2019年3月27日
  3. 模型 - IBIS
    英语
    RMQC4A1818DGBA-302 Verilog model for VCS (vcs_rmqc4a1818.vp)
    登录后下载 VP 100 KB D6003500 日本語 2019年3月27日
  4. 模型 - IBIS
    英语
    RMQC4A1818DGBA-302 IBIS (rmqc4a1818dgba.ibs)
    登录后下载 IBS 1.79 MB D3015645 日本語 2015年4月01日
加载中
加载中加载中