封装信息
环境和出口类别
| RoHS (D6417750RBP200DV) | 英语日文 |
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | |
| ECCN (US) | |
| HTS (US) |
产品属性
| CPU | SH-4 |
| Bit Size | 32 |
| Operating Freq (Max) (MHz) | 200 |
| Timer | 32-bit x 5-ch |
| DMA | No |
| Ethernet | No |
| RTC | Yes |
| LVD or PVD | No |
| Temp. Range | -40 to +85°C |
| Family Name | SuperH |
| Lead Compliant | No |
| MOQ | 1 |
| Pb (Lead) Free | Yes |
| Tape & Reel | No |
描述
The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache. The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.