概览
描述
14-bit registered buffer designed for 2.3V-2.7V. VDD for PC1600-PC2700, and 2.5V-2.7V VDD for PC3200, and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.
特性
- 1:1 registered buffer
- Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857
- 2.3V to 2.7V operation for PC1600, PC2100, and PC2700
- 2.5V to 2.7V operation for PC3200
- SSTL_2 Class II style data inputs/outputs
- Differential CLK input
- RESET control compatible with LVCMOS levels
- Flow-through architecture for optimum PCB design
- Drive up to equivalent of 18 SDRAM loads
- Latch-up performance exceeds 100mA
- ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
- Available in TSSOP package
产品对比
应用
设计和开发
模型
ECAD 模块
点击产品选项表中的 CAD 模型链接，查找 SamacSys 中的原理图符号、PCB 焊盘布局和 3D CAD 模型。如果符号和模型不可用，可直接在 SamacSys 请求该符号或模型。
