时钟和时序

概览

The IDT8T49N366I integrates low phase noise Frequency Translation / Synthesis and Jitter attenuation. It includes alarm and monitoring functions suitable for networking and communications applications. The device has three fully independent PLLs. Each PLL is able to generate any output frequency in the 0.98MHz - 312.5MHz range and most output frequencies in the 312.5MHz - 1,300MHz range. A wide range of input reference clocks may be used as the source for the output frequency. Each PLL of IDT8T49N366I has three operating modes to support a very broad spectrum of applications: Frequency Synthesizer, High-Bandwidth Frequency Translator and Low-Bandwidth Frequency Translator.
 
To see other devices in this product family, visit the Universal Frequency Translators page.
 
8T49N366I - Block Diagram
8T49N366I - Pinout
8T49N366I - Block Diagram
8T49N366I - Pinout
  • Three fully independent PLLs
  • Input frequency range: 8kHz - 710MHz
  • Outputs are programmable as LVPECL or LVDS
  • Programmable output frequency: 0.98MHz up to 1,300MHz
  • Two differential inputs per PLL support the following input types: LVPECL, LVDS, LVHSTL, HCSL
  • I2C Serial interface for register programming
  • RMS phase jitter: 465fs (typical), Low Bandwidth Mode (FracN)
  • RMS phase jitter: 333fs (typical), Synthesizer Mode (Integer FB)
  • Full 2.5V ±5% supply mode
  • -40°C to 85°C ambient operating temperature
  • 10mm x 10mm CABGA lead-free (RoHS 6) package
  • Additional Family members include a Dual PLL device, 8T49N244I, and QUAD PLL devices 8T49N445I and 8T49N488I
 

文档

文档标题 类型 日期
IDT8T49N366I Datasheet
PDF592 KB
数据手册
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
应用文档
AN-828 Termination - LVPECL
PDF322 KB
应用文档
AN-831 The Crystal Load curve
PDF395 KB
应用文档
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
应用文档
AN-846 Termination - LVDS
PDF133 KB
应用文档
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
应用文档
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
应用文档
AN-838 Peak-to-Peak Jitter Calculations
PDF115 KB
应用文档
AN-839 RMS Phase Jitter
PDF233 KB
应用文档
AN-832 Timing Budget and Accuracy
PDF131 KB
应用文档
AN-833 Differential Input Self Oscillation Prevention
PDF180 KB
应用文档
AN-834 Hot-Swap Recommendations
PDF153 KB
应用文档
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
应用文档
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
应用文档
AN-830 Quartz Crystal Drive Level
PDF143 KB
应用文档
AN-815 Understanding Jitter Units
PDF565 KB
应用文档
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF136 KB
应用文档
AN-801 Crystal-High Drive Level
PDF202 KB
应用文档
AN-805 Recommended Ferrite Beads
PDF121 KB
应用文档
AN-806 Power Supply Noise Rejection
PDF438 KB
应用文档
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products
PDF108 KB
应用文档
FemtoNG Universal Frequency Translator Ordering Product Information Guide
PDF270 KB
手册 - 硬件
Jitter Attenuator Product Overview
PDF1.62 MB
概览
PCN# : W1308-01 Change of Passivation Thickness
PDF941 KB
产品变更通告

设计和开发

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    Processing table
    器件号
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    购买 / 样片
    8T49N366A-000ASGI
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    8T49N366A-999ASGI
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    		CABGA 80 I Yes Reel
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    新闻和博客

    Benefits of a Point-of-Use Clock for Jitter Optimization 博客 2021年4月27日