概览
描述
The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.
特性
- Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns
- One Chip Select plus one Output Enable pin
- Bidirectional data inputs and outputs directly LVTTL-compatible
- Low power consumption via chip deselect
- Upper and Lower Byte Enable Pins
- Single 3.3V power supply
- Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages
产品对比
应用
设计和开发
模型
ECAD 模块
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