概览

简介

The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.

特性

  • JEDEC revolutionary pinout (center power/GND) for reduced noise
  • Equal access and cycle times – Commercial: 10/12/15/20ns – Industrial: 10/12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Inputs and outputs are LVTTL-compatible
  • Single 3.3V supply
  • Low power consumption via chip deselect
  • Available in 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages.

Comparison

应用

文档

设计和开发

模型