概览

描述

The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

特性

  • High performance system speed - 150MHz (3.8ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%)
  • 3.3V I/O Supply (VDDQ)
  • Power down controlled by ZZ input
  • Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages

文档

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数据手册
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应用文档
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器件勘误表
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设计和开发

模块

模块

Title Type Date
模型 - IBIS

支持