概览
描述
This is the evaluation kit for the Renesas 8A34001 ClockMatrix System Synchronizer for IEEE 1588. The 8A34001 provides eight independent timing channels that can be configured as Digital PLLs (DPLLs) or as Digitally Controlled Oscillators (DCOs). The DPLL channels meet synchronous Ethernet requirements and they can be used for jitter attenuation and frequency translation. The DCOs they can be programmed to synthesize the desired frequency and can be steered by external software with resolution of 1.11E-16. The DPLLs can lock to virtually any frequency from 0.5Hz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with typical jitter below 150fs RMS from 12kHz to 20MHz.
特性
- 8 differential clock inputs
- 12 differential outputs
- 2 serial port channels
- On-board EEPROM
- On-board miniOCXO
- 16 GPIO controls
- Selectable voltage controls
应用
设计和开发
模型
ECAD 模块
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